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A cycle-accurate 6502 CPU core for FPGAs and ASICs, including peripherals

4 starsPython

m6502, a 6502 CPU for FPGAs and Tiny Tapeout

by chrismoos·Feb 18, 2026·5 points·1 comment
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AI Analysis

●●●●GemWizardryZero to OneNiche Gem

Cycle-accurate 6502 core at ~950 LUTs, shipping to real silicon via Tiny Tapeout.

Strengths
  • •Real silicon outcome: scheduled for IHP26a tapeout, not vaporware—moves past "runs on FPGA" to actual ASIC deployment
  • •Genuine architecture insight: vertical microcode for minimal gate count (950 LUTs) + RP2040 bus mux solves pin constraints elegantly—not a brute-force approach
  • •100% MOS 6502 compatibility claim with cycle accuracy is non-trivial—enables real Apple II software, not simulation
Weaknesses
  • •Author hedges: "should be 100% compatible, would need to still test"—foundational claim untested at submission
  • •Extremely niche: requires SystemVerilog, FPGA toolchain knowledge, and Tiny Tapeout participation; most devs won't use this
Category
Hardware
Target Audience

FPGA hobbyists, Tiny Tapeout participants, retro computing enthusiasts, chip design learners

Similar To

Visual6502 · MAME 6502 emulation · previous Tiny Tapeout CPU submissions

Post Description

Hey HN,

Recently built an Apple II emulator and at the same time was getting into Tiny Tapeout and decided it would be cool to build a cycle-accurate 6502 CPU and an MCU for it. It's cycle accurate and the core itself should be 100% compatible with a stock MOS 6502 (would need to still test this though!).

Tested on some FPGAs (fomu, ulx3s) and works great, hoping to get it taped out in the upcoming IHP26a shuttle.

Also as part of the project I built a bus multiplexer to allow memory/bus access from an RP2040 to work around the limited pin count on Tiny Tapeout. This let's you load up programs on RP2040 and the CPU can read/write from it.

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