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ML accelerator on a RISC-V FPGA SoC – zero-cycle matmul, boots Linux

ML accelerator on a RISC-V FPGA SoC – zero-cycle matmul, boots Linux

by dstrbad·Mar 20, 2026·4 points·0 comments
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AI Analysis

●●SolidWizardryBig BrainNiche Gem

Zero-cycle matrix multiplication in combinatorial logic on Lattice ECP5 is genuinely wild.

Strengths
  • •Combinatorial logic matmul at zero-cycle latency is a clever hardware optimization
  • •Full RISC-V SoC booting Linux 6.9 on ULX3S shows serious FPGA chops
  • •Transparent build log documenting architecture decisions and failures
Weaknesses
  • •This is a blog post about work-in-progress, not a shippable tool or library
  • •No code repository linked, just documentation of ongoing experiments
Category
Hardware
Target Audience

FPGA developers, edge ML engineers, hardware hackers

Similar To

Google TPU · Groq LPU · Mythic AI

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