Hardware●●Solid
ML accelerator on a RISC-V FPGA SoC – zero-cycle matmul, boots Linux
Zero-cycle matrix multiplication in combinatorial logic on Lattice ECP5 is genuinely wild.
WizardryBig BrainNiche Gem
dstrbad
402mo ago
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I designed a 24-trit balanced ternary RISC processor on FPGA
by claudio_mos·Mar 24, 2026·1 point·3 comments
AI Analysis
●●●●GemWizardryBig Brain
24-trit balanced ternary RISC processor on FPGA is hardware wizardry.
Strengths
- •Balanced ternary logic is a rare, fascinating architectural choice.
- •Full RISC implementation on FPGA demonstrates deep hardware engineering.
Weaknesses
- •Zenodo 403 errors create friction for curious developers trying to access.
- •Niche architecture has limited practical application outside education.
Category
Target Audience
Hardware engineers, FPGA hobbyists, CS students
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Ben Eater's 8-bit computer · RISC-V implementations · FPGA cores
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