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Verified 16.7M Mac chip architecture on $60 Android phone

Verified 16.7M Mac chip architecture on $60 Android phone

by jltackett·Feb 18, 2026·3 points·0 comments
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AI Analysis

○PassWizardryDark HorseNiche Gem
The Take

Simulating a 16,777,216-MAC analog in-memory Phoenix SoC on a $60 Android using iverilog and Yosys is an audacious technical flex — the repo claims end-to-end verification (adders → ALUs → RISC‑V core → FPU) and a working 8-bit CPU. It's simulation-only and the writeup could do more to make reproduction trivial, but the ULA plain-English compiler and the no-cloud, mobile-only build story make this a rare outsider contribution to EDA.

Category
Hardware
Target Audience

Chip designers, semiconductor / EDA engineers, RISC‑V and hardware hackers, systems architects interested in in-memory compute

Post Description

Over 6 weeks I built and verified a complete chip architecture on a $60 Android phone using Termux, iverilog, and Yosys.

Phoenix 4096×4096 specs: - 16,777,216 MAC units (analog in-memory compute) - 50,331 TOPS @ 3GHz (25× NVIDIA H100) - 512 deterministic reasoning cores - 2 TB/s memory bandwidth - All verified in simulation

Hardware verified (15/15 passing): - Half Adder → Full Adder → 8/16/64/128/256-bit ALUs - 8-bit CPU (Fibonacci working) - RISC-V core - FPU (IEEE 754) - GPU SIMD - Complete Phoenix SoC

Also built: - ULA compiler: Plain English → 12 languages (Python, Rust, Java, Assembly, COBOL, Fortran, C, C++, Go, Kotlin, Solidity, TypeScript) - RF presence detection: 2-person tracking via WiFi signals, no cameras, 91% gesture accuracy

All code on GitHub: https://github.com/jltackett1980-cell

Built in Sikeston, MO on a $60 Android. No laptop. No cloud. No funding.

Looking for: Chip designers, semiconductor engineers, anyone interested in open silicon or analog computing. Want to tape out with Efabless or similar.

Live demo available

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