Open-source logic synthesis – formal logic to FPGA
Open-source logic synthesis running on FPGAs when Yosys dominates the space.
Formally verified FPGA watchdog for critical AM broadcast proves hardware safety via math, not testing.
Emergency comms engineers, tunnel operators, RF engineers working in confined spaces with specific regulatory needs
Open-source logic synthesis running on FPGAs when Yosys dominates the space.
First formally verified polygon intersection with Lean 4 proof and web demo.
TLA+ verification caught production bugs that years of testing missed.
First formally verified polygon intersection—Lean 4 proofs guarantee correctness for all inputs.
Formal verification for LLM workflows—CTL model checking, Z3 proofs, zero hallucination math.
Rust-style channel patterns fill gaps Go's native channels leave open.