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Open-source logic synthesis – formal logic to FPGA

Open-source logic synthesis – formal logic to FPGA

by major4x·Mar 27, 2026·1 point·0 comments
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AI Analysis

●●●BangerZero to OneWizardryBold Bet

Open-source logic synthesis running on FPGAs when Yosys dominates the space.

Strengths
  • •Unifies Boolean formulas, QBF, and circuits under a single representation library.
  • •Proven on hardware: 16x16 integer factorization on Xilinx Artix-7 FPGAs.
  • •Custom Verilog parser and AST for programmatic inspection and transformation.
Weaknesses
  • •Extremely niche audience; requires deep digital design knowledge to use effectively.
  • •Early ecosystem; lacks the optimization maturity of commercial EDA suites.
Target Audience

Hardware engineers, FPGA developers, PL researchers

Similar To

Yosys · Berkeley ABC · Symbiflow

Post Description

Happy to answer questions about the architecture, the QBF synthesis approach, or the FPGA implementation. Repos: https://gitlab.llama.gs/logic

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